Conventionally, track-width and back-edge definitions of GMR heads are fabricated in two separate steps. As illustrated in FIG. 1, track width 11b is formed first through a lithographic process, followed by ion beam etching, ion beam deposition of dielectric materials, and lift-off of photo resists. Back-edge is patterned next by following the similar processes with mask 11c across the track width, as shown in FIG. 2.
FIG. 3 is a schematic representation of the area contained within circle 22, As the CPP sensor size is shrunk to below 100 nm, this conventional two-step process becomes a challenge. As noted in the area of a, b, and c in FIG. 3, such a process can produce an uneven etch-depth of dielectric materials around the sensor and cause shorting to the overlay top lead layer. One way to overcome this problem is to combine the two-step process into one by using stencil mask 41 shown in FIG. 4, which extends beyond the final location of ABS (air bearing surface) 42. However, such modification can produce undesirable round back-edge corners 51 (as illustrated in FIG. 5). The present invention discloses an approach to resolving this problem.
In addition, conventional liftoff resist patterning procedures that employ dual-layer resists are very difficult to apply to the production of sub-100 nm resist features. The main problem lies in the very narrow process window available for undercut control. Undercut control using a thin release layer can result in liftoff difficulty. On the other hand, if the undercut is too large, it can cause collapse of the top image layer. The present invention discloses a process that eliminates the need for a liftoff mask for defining the most critical width of the structure.
A routine search of the prior art was performed with the following references of interest being found:
U.S. Pat. No. 6,462,915 (Sasaki) discloses electroless plating of a permalloy to form the bottom pole of a CPP device.n while U.S. Pat. No. 6,419,845 (Sasaki) shows a NiB plating layer.